| Pin No. |
符號 |
輸入/輸出 |
功能說明 |
| 1~2 |
IF1~IF2 |
I |
Input data format control |
| 3 |
POL |
O |
Polarity Signal connect to VCOM driving circuit. |
| 4 |
RESET |
I |
Hardware reset. |
| 5 |
SPENA |
I |
Chip select |
| 6 |
SPCL |
I |
Serial Clock |
| 7 |
SPDA |
I/O |
Serial Data |
| 8 |
B0 |
I |
Blue Data bit (LSB) |
| 9~14 |
B1~B6 |
I |
Blue Data bit |
| 15 |
B7 |
I |
Blue Data bit(MSB) |
| 16 |
G0 |
I |
Green Data bit(LSB) |
| 17~22 |
G1~G6 |
I |
Green Data bit |
| 23 |
G7 |
I |
Green Data bit(MSB) |
| 24 |
R0 |
I |
Red Data bit(LSB) |
| 25~30 |
R1~R6 |
I |
Red Data bit |
| 31 |
R7 |
I |
Red Data bit(MSB) |
| 32 |
Hsync |
I |
Horizontal synchronous signal |
| 33 |
Vsync |
I |
Vertical synchronous signal |
| 34 |
Data CLK |
I |
Dot data clock |
| 35~36 |
AVDD |
I |
4.5V~5.5V |
| 37~38 |
Vcc |
I |
3V~3.6V |
| 39 |
NPC |
O |
NTSC/PAL mode Auto detection result H:NTSC/L:PAL |
| 40~41 |
VGL |
I |
Gate off power |
| 42 |
UD |
I |
Up/Down scan setting. H: Reverse scan / L: Normal scan |
| 43 |
VGH |
I |
Gate on power |
| 44 |
LRC |
I |
Shift direction of device internal shift register control. |
| 45 |
GND |
I |
GROUND |
| 46~47 |
VCOM |
I |
VCOM driving input |
| 48 |
ENB |
I |
Data enable input. Normally pull low. |
| 49~50 |
GND |
I |
GROUND |